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data sheet 10.97 mi c r o c omp u ter componen t s c515a 8-bit cmos microcontroller
c515a data sheet revision history: current version: 10.97 previous version: none page (in previous version) page (in current version) subjects (major changes since last revision) edition 10.97 published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra? 73, 81541 m?nchen siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ?get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered.
semiconductor group 3 1997-10-01 8-bit cmos microcontroller advance information c515a full upward compatibility with sab 80c515a/83c515a-5 up to 24 mhz external operating frequency 500 ns instruction cycle at 24 mhz operation 32k byte on-chip rom (with optional rom protection) alternatively up to 64k byte external program memory up to 64k byte external data memory 256 byte on-chip ram 1k byte on-chip ram (xram) six 8-bit parallel i/o ports one input port for analog/digital input full duplex serial interface (usart) 4 operating modes, fixed or variable baud rates three 16-bit timer/counters timer 0 / 1 (c501 compatible) timer 2 for 16-bit reload, compare, or capture functions (further features are on next page) figure 1 c515a functional units i / o mca03239 rom ram xram cpu usart i / o i / o i / o timer watchdog i / o i / o analog / digital input watchdog oscillator a / d converter 10-bit support module on-chip emulation power saving modes port 3 port 2 port 1 port 0 port 4 port 5 port 6 t 1 t 0 t 2 1 k x 8 256 x 8 32 k x 8
c515a semiconductor group 4 1997-10-01 features (cont?): 10-bit a/d converter 8 multiplexed analog inputs built-in self calibration 16-bit watchdog timer power saving modes slow down mode idle mode (can be combined with slow down mode) software power down mode with wake-up capability through int0 pin hardware power down mode 12 interrupt sources (7 external, 5 internal) selectable at 4 priority levels ale switch-off capability on-chip emulation support logic (enhanced hooks technology tm ) p-mqfp-80-1 package temperature ranges: sab-c515a t a = 0 to 70 c saf-c515a t a = ?40 to 85 c sah-c515a t a = ?40 to 85 c sak-c515 t a = ?40 to 110 c (max. operating frequency: 18 mhz) the c515a is an upward compatible version of the sab 80c515a/83c515a-5 8-bit microcontroller which additionally provides an improved 10-bit a/d converter, ale switch-off capability, on-chip emulation support, rom protection, and enhanced power saving mode capabilities. with a maximum external clock rate of 24 mhz it achieves a 500 ns instruction cycle time (1 m s at 12 mhz). the c515a is mounted in a p-mqfp-80 package. note: versions for extended temperature ranges ?40 c to 110 c and ?40 c to 125 c (sah-c515a and sak-c515a) are available on request. the ordering number of rom types (dxxxx extensions) is defined after program release (verification) of the customer. ordering information type ordering code package description (8-bit cmos microcontroller) sab-c515a-4rm q67121-dxxxx p-mqfp-80-1 with mask programmable rom (18 mhz) saf-c515a-4rm q67121-dxxxx p-mqfp-80-1 with mask programmable rom (18 mhz) ext. temp. ?40 c to 85 c sab-c515a-4r24m q67121-dxxxx p-mqfp-80-1 with mask programmable rom (24 mhz) saf-c515a-4r24m q67121-dxxxx p-mqfp-80-1 with mask programmable rom (24 mhz) ext. temp. ?40 c to 85 c sab-c515a-lm Q67121-C1068 p-mqfp-80-1 for external memory (18 mhz) saf-c515a-lm q67121-c1069 p-mqfp-80-1 for external memory (18 mhz) ext. temp. ?40 c to 85 c sab-c515a-l24m q67121-c1070 p-mqfp-80-1 for external memory (24 mhz) saf-c515a-l24m q67127-c2020 p-mqfp-80-1 for external memory (24 mhz) ext. temp. ?40 c to 85 c
semiconductor group 5 1997-10-01 c515a figure 2 logic symbol additional literature for further information about the c515a the following literature is available: title ordering number c515a 8-bit cmos microcontroller user? manual b158-h7051-x-x-7600 c500 microcontroller family architecture and instruction set user? manual b158-h6987-x-x-7600 c500 microcontroller family - pocket guide b158-h6986-x-x-7600 agnd aref v v hwpd reset pe / swd psen ea ale xtal2 xtal1 digital input 8-bit analog / 8-bit digit. i / o port 6 port 5 v ss v cc c515a mcl03240 8-bit digit. i / o port 4 8-bit digit. i / o port 3 8-bit digit. i / o port 2 8-bit digit. i / o port 1 8-bit digit. i / o port 0
c515a semiconductor group 6 1997-10-01 figure 3 pin configuration p-mqfp-80 package (top view) p5.7 p0.7 / ad7 p0.5 / ad5 p0.6 / ad6 ea p0.0 / ad0 p0.1 / ad1 p2.7 / a15 p2.6 / a14 psen n.c. ale p5.0 p5.5 p5.6 p5.4 p5.3 p5.1 p5.2 p4.4 p4.3 n.c. hwpd p3.2 / int0 n.c. p6.6 / ain6 p6.4 / ain4 p6.5 / ain5 p6.7 / ain7 reset p1.7 / t2 p1.6 / clkout p1.5 / t2ex p1.4 / int2 p1.0 / int3 / cc0 xtal2 xtal1 p2.1 / a9 p2.2 / a10 mcp03241 p0.4 / ad4 p0.3 / ad3 p0.2 / ad2 p6.3 / ain3 p6.2 / ain2 p6.1 / ain1 p3.0 / rxd p3.1 / txd p2.0 / a8 c515a 60 61 80 21 40 70 30 41 50 20 10 1 p3.5 / t1 p3.4 / t0 p3.3 / int1 n.c. n.c. p4.7 p4.6 p4.5 p2.3 / a11 p2.4 / a12 p2.5 / a13 p3.6 / wr n.c. p3.7 / rd p1.1 / int4 / cc1 p1.2 / int5 / cc2 v aref v agnd p6.0 / ain0 n.c. p1.3 / int6 / cc3 v cc v cc v ss v ss n.c. n.c. n.c. p4.0 / adst p4.1 p4.2 pe / swd 23456789 13 11 12 14 15 16 17 18 19 22 23 24 25 26 27 28 29 32 31 39 38 37 36 35 34 33 42 43 44 45 46 47 48 49 54 59 58 56 57 55 52 53 51 62 63 64 65 66 67 68 69 79 74 78 77 76 75 73 72 71
semiconductor group 7 1997-10-01 c515a table 1 pin de?itions and functions symbol pin number (p-mqfp-80) i/o*) function p4.0-p4.7 72-74, 76-80 72 i/o port 4 is an 8-bit quasi-bidirectional i/o port with internal pull- up resistors. port 4 pins that have 1? written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inputs, port 4 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pull-up resistors. p4 also contains the external a/d converter control pin. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the secondary function is assigned to port 6 as follows: p4.0 / adst external a/d converter start pin pe /swd 75 i power saving mode enable / start watchdog timer a low level on this pin allows the software to enter the power down, idle, and slow down mode. in case the low level is also seen during reset, the watchdog timer function is off on default. use of the software controlled power saving modes is blocked when this pin is held on high level. a high level during reset performs an automatic start of the watchdog timer immediately after reset. when left unconnected this pin is pulled high by a weak internal pull-up resistor. note: if pe /swd is low and v aref is low the oscillator watchdog is disabled (testmode)! reset 1i reset a low level on this pin for the duration of two machine cycles while the oscillator is running resets the c515a. a small internal pullup resistor permits power-on reset using only a capacitor connected to v ss . varef 3 reference voltage for the a/d converter vagnd 4 reference ground for the a/d converter p6.0-p6.7 12-5 i port 6 is an 8-bit unidirectional input port to the a/d converter. port pins can be used for digital input, if voltage levels simultaneously meet the specifications for high/low input voltages and for the eight multiplexed analog inputs. *) i = input o = output
c515a semiconductor group 8 1997-10-01 p3.0-p3.7 15-22 15 16 17 18 19 20 21 22 i/o port 3 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 3 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the secondary functions are assigned to the pins of port 3, as follows: p3.0 / rxd receiver data input (asynch.) or data input/output (synch.) of serial interface p3.1 / txd transmitter data output (asynch.) or clock output (synch.) of serial interface p3.2 / int0 external interrupt 0 input / timer 0 gate control input p3.3 / int1 external interrupt 1 input / timer 1 gate control input p3.4 / t0 timer 0 counter input p3.5 / t1 timer 1 counter input p3.6 / wr wr control output; latches the data byte from port 0 into the external data memory p3.7 / rd rd control output; enables the external data memory *) i = input o = output table 1 pin de?itions and functions (cont?) symbol pin number (p-mqfp-80) i/o*) function
semiconductor group 9 1997-10-01 c515a p1.0 - p1.7 31-24 31 30 29 28 27 26 25 24 i/o port 1 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 1 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. the port is used for the low-order address byte during program verification. port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). the secondary functions are assigned to the port 1 pins as follows: p1.0 / int3 / cc0 interrupt 3 input / compare 0 output / capture 0 input p1.1 / int4 / cc1 interrupt 4 input / compare 1 output / capture 1 input p1.2 / int5 / cc2 interrupt 5 input / compare 2 output / capture 2 input p1.3 / int6 / cc3 interrupt 6 input / compare 3 output / capture 3 input p1.4 / int2 interrupt 2 input p1.5 / t2ex timer 2 external reload / trigger input p1.6 / clkout system clock output p1.7 / t2 counter 2 input v cc 32, 33 supply voltage during normal, idle, and power down mode. v ss 34, 35 ground (0v) during normal, idle, and power down operation. *) i = input o = output table 1 pin de?itions and functions (cont?) symbol pin number (p-mqfp-80) i/o*) function
c515a semiconductor group 10 1997-10-01 xtal2 36 xtal2 input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal2 should be driven, while xtal1 is left unconnected. minimum and maximum high and low times as well as rise/fall times specified in the ac characteristics must be observed. xtal1 37 xtal1 output of the inverting oscillator amplifier. p2.0-p2.7 38-45 i/o port 2 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 2 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pullup resistors when issuing 1's. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 issues the contents of the p2 special function register. psen 47 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every six oscillator periods, except during external data memory accesses. the signal remains high during internal program execution. ale 48 o the address latch enable output is used for latching the address into external memory during normal operation. it is activated every six oscillator periods, except during an external data memory access. ale can be switched off when the program is executed internally. *) i = input o = output table 1 pin de?itions and functions (cont?) symbol pin number (p-mqfp-80) i/o*) function
semiconductor group 11 1997-10-01 c515a ea 49 i external access enable when held high, the c515a executes instructions from the internal rom (c515a-4r) as long as the pc is less than 8000 h . when held low, the c515a fetches all instructions from external program memory. for the c515a-l this pin must be tied low. p0.0-p0.7 52-59 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pullup resistors when issuing 1's. port 0 also outputs the code bytes during program verification in the c515a-4r. external pullup resistors are required during program verification. p5.0-p5.7 67-60 i/o port 5 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 5 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. hwpd 69 i hardware power down a low level on this pin for the duration of one machine cycle while the oscillator is running resets the c515a. a low level for a longer period will force the c515a into hardware power down mode with the pins floating. n.c. 2, 13, 14, 23, 46, 50, 51, 68, 70, 71 not connected these pins of the p-mqfp-80 package need not be connected. *) i = input o = output table 1 pin de?itions and functions (cont?) symbol pin number (p-mqfp-80) i/o*) function
c515a semiconductor group 12 1997-10-01 figure 4 block diagram of the c515a cpu watchdog oscillator port 5 port 4 port 3 port 2 port 1 8-bit digit. i / o port 0 ram xram rom programmable watchdog timer usart generator interrupt unit 10-bit a/d converter emulation support logic port 0 port 1 port 2 port 3 port 4 port 5 port 6 osc & timing port 6 s&h mux analog xtal1 xtal2 ale psen ea pe / swd reset hwpd v aref agnd v 8-bit analog / digital input c515a mcb03242 1 k x 8 32 k x 8 256 x 8 timer 0 timer 1 timer 2 baud rate 8-bit digit. i / o 8-bit digit. i / o 8-bit digit. i / o 8-bit digit. i / o 8-bit digit. i / o
semiconductor group 13 1997-10-01 c515a cpu the c515a is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. with a 18 mhz crystal, 58% of the instructions are executed in 666 ns ( 24 mhz : 500 ns). special function register psw (address d0 h ) reset value : 00 h bit function cy carry flag used by arithmetic instruction. ac auxiliary carry flag used by instructions which execute bcd operations. f0 general purpose flag rs1 rs0 register bank select control bits these bits are used to select one of the four register banks. ov overflow flag used by arithmetic instruction. f1 general purpose flag p parity flag set/cleared by hardware after each instruction to indicate an odd/even number of ?ne?bits in the accumulator, i.e. even parity. cy ac f0 rs1 rs0 ov f1 p d0 h psw d7 h d6 h d5 h d4 h d3 h d2 h d1 h d0 h bit no. msb lsb rs1 rs0 function 0 0 bank 0 selected, data address 00 h -07 h 0 1 bank 1 selected, data address 08 h -0f h 1 0 bank 2 selected, data address 10 h -17 h 1 1 bank 3 selected, data address 18 h -1f h
c515a semiconductor group 14 1997-10-01 memory organization the c515a cpu manipulates operands in the following five address spaces: up to 64 kbyte of program memory (32k on-chip program memory for c515a-4r) up to 64 kbyte of external data memory 256 bytes of internal data memory 1k bytes of internal xram data memory a 128 byte special function register area figure 5 illustrates the memory address spaces of the c515a. figure 5 c515a memory map ext. int. ea = 1) ext. data memory internal xram (1 kbyte) ext. ffff h 8000 h 7fff h 0000 h data memory ext. fc00 h 00 h h 7f regs. function special ram internal ram internal h 80 h ff addr. indirect addr. direct alternatively "code space" "data space" "internal data space" mcb03243 ea = 1) ffff h h 0000 fbff h
semiconductor group 15 1997-10-01 c515a reset and system clock the reset input is an active low input at pin reset . since the reset is synchronized internally, the reset pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. a pullup resistor is internally connected to v cc to allow a power-up reset with an external capacitor only. an automatic reset can be obtained when v cc is applied by connecting the reset pin to v ss via a capacitor. figure 6 shows the possible reset circuitries. figure 6 reset circuitries
c515a semiconductor group 16 1997-10-01 figure 7 shows the recommended oscillator circuitries for crystal and external clock operation. figure 7 recommended oscillator circuitries mcs03245 c c 3.5 - 24 mhz xtal1 xtal2 xtal2 xtal1 n.c. external oscillator signal crystal oscillator mode driving from external source crystal mode: c = 20 pf 10 pf (incl. stray capacitance)
semiconductor group 17 1997-10-01 c515a enhanced hooks emulation concept the enhanced hooks emulation concept of the c500 microcontroller family is a new, innovative way to control the execution of c500 mcus and to gain extensive information on the internal operation of the controllers. emulation of on-chip rom based programs is possible, too. each production chip has built-in logic for the support of the enhanced hooks emulation concept. therefore, no costly bond-out chips are necessary for emulation. this also ensure that emulation and production chips are identical. the enhanced hooks technology tm 1) , which requires embedded logic in the c500 allows the c500 together with an eh-ic to function similar to a bond-out chip. this simplifies the design and reduces costs of an ice-system. ice-systems using an eh-ic and a compatible c500 are able to emulate all operating modes of the different versions of the c500 microcontrollers. this includes emulation of rom, rom with code rollover and romless modes of operation. it is also able to operate in single step mode and to read the sfrs after a break. figure 8 basic c500 mcu enhanced hooks concept configuration port 0, port 2 and some of the control lines of the c500 based mcu are used by enhanced hooks emulation concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ice-system) and the c500 mcu. 1 ?nhanced hooks technology?is a trademark and patent of metalink corporation licensed to siemens. syscon pcon tcon reset ea ale psen port 0 port 2 port 1 port 3 opt. i/o ports c500 mcu 2 rpcon rtcon enhanced hooks interface circuit rsyscon 0 rport rport tea tale tpsen eh-ic ice-system interface to emulation hardware target system interface mcs03254
c515a semiconductor group 18 1997-10-01 special function registers the registers, except the program counter and the four general purpose register banks, reside in the special function register area. the special function register area consists of two portions: the standard special function register area and the mapped special function register area. one special function register of the c515a (pcon1) is located in the mapped special function register area. for accessing this mapped special function register, bit rmap in special function register syscon must be set. all other special function registers are located in the standard special function register area which is accessed when rmap is cleared (??. special function register syscon (address b1 h ) reset value : xx10xx01 b as long as bit rmap is set, the mapped special function register area (sfr pcon1) can be accessed. this bit is not cleared by hardware automatically. thus, when non-mapped/mapped registers are to be accessed, the bit rmap must be cleared/set respectively by software. the 49 special function registers (sfrs) in the standard and mapped sfr area include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. all sfrs with addresses where address bits 0-2 are 0 (e.g. 80 h , 88 h , 90 h , 98 h , ? f8 h , ff h ) are bitaddressable. the sfrs of the c515a are listed in table 2 and table 3 . in table 2 they are organized in groups which refer to the functional blocks of the c515a. table 3 illustrates the contents of the sfrs in numeric order of their addresses. bit function rmap special function register map bit rmap = 0: the access to the non-mapped (standard) special function register area is enabled. rmap = 1: the access to the mapped special function register area (sfr pcon1) is enabled. reserved bits for future use. read by cpu returns undefined values. 76543210 eale rmap b1 h syscon bit no. msb lsb xmap1 xmap0 the functions of the shaded bits are not described in this section.
semiconductor group 19 1997-10-01 c515a table 2 special function registers - functional blocks block symbol name address contents after reset cpu acc b dph dpl psw sp syscon 2) accumulator b-register data pointer, high byte data pointer, low byte program status word register stack pointer system/xram control register e0 h 1) f0 h 1) 83 h 82 h d0 h 1) 81 h b1 h 00 h 00 h 00 h 00 h 00 h 07 h xx10 xx01 b 3) a/d- converter adcon0 2) adcon1 addath addatl a/d converter control register 0 a/d converter control register 1 a/d converter data register, high byte a/d converter data register, low byte d8 h 1) dc h d9 h da h 4) 00 h 0xxx x000 b 3) 00 h 00xx xxxx b 3) interrupt system ien0 2) ien1 2) ip0 2) ip1 2) ircon tcon 2) t2con 2) scon 2) interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 interrupt priority register 1 interrupt request control register timer control register timer 2 control register serial channel control register a8 h 1) b8 h 1) a9 h b9 h c0 h 1) 88 h 1) c8 h 1) 98 h 1) 00 h 00 h 00 h xx00 0000 b 3) 00 h 00 h 00 h 00 h timer 0/ timer 1 tcon 2) th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h compare/ capture unit / timer 2 ccen cch1 cch2 cch3 ccl1 ccl2 ccl3 crch crcl th2 tl2 t2con 2) comp./capture enable reg. comp./capture reg. 1, high byte comp./capture reg. 2, high byte comp./capture reg. 3, high byte comp./capture reg. 1, low byte comp./capture reg. 2, low byte comp./capture reg. 3, low byte com./rel./capt. reg. high byte com./rel./capt. reg. low byte timer 2, high byte timer 2, low byte timer 2 control register c1 h c3 h c5 h c7 h c2 h c4 h c6 h cb h ca h cd h cc h c8 h 1) 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) ??means that the value is undefined and the location is reserved
c515a semiconductor group 20 1997-10-01 ports p0 p1 p2 p3 p4 p5 p6 port 0 port 1 port 2 port 3 port 4 port 5 port 6, analog/digital input 80 h 1) 90 h 1) a0 h 1) b0 h 1 e8 h 1) f8 h 1) db h ff h ff h ff h ff h ff h ff h xram xpage syscon 2) page address register for extended on-chip ram system/xram control register 91 h b1 h 00 h xx10 xx01 b 3) serial channel adcon0 2) pcon 2) sbuf scon 2) srell srelh a/d converter control register power control register serial channel buffer register serial channel control register serial channel reload register, low byte serial channel reload register, high byte d8 h 1 87 h 99 h 98 h 1) aa h ba h 00 h 00 h xx h 3) 00 h d9 h xxxx xx11 b 3) watchdog ien0 2) ien1 2) ip0 2)) ip1 2) wdtrel interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 interrupt priority register 1 watchdog timer reload register a8 h 1) b8 h 1) a9 h b9 h 86 h 00 h 00 h 00 h xx00 0000 b 3) 00 h power saving modes pcon 2) pcon1 4) power control register power control register 1 87 h 88 h 00 h 0xxx xxxx b 3) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) ??means that the value is undefined and the location is reserved. 4) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. table 2 special function registers - functional blocks (cont?) block symbol name address contents after reset
semiconductor group 21 1997-10-01 c515a table 3 contents of the sfrs, sfrs in numeric order of their addresses addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h 2) p0 ff h .7 .6 .5 .4 .3 .2 .1 .0 81 h sp 07 h .7 .6 .5 .4 .3 .2 .1 .0 82 h dpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h dph 00 h .7 .6 .5 .4 .3 .2 .1 .0 86 h wdtrel 00 h wdt psel .6 .5 .4 .3 .2 .1 .0 87 h pcon 00 h smod pds idls sd gf1 gf0 pde idle 88 h 2) tcon 00 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88 h 3) pcon1 0xxx- xxxx b ewpd 89 h tmod 00 h gate c/t m1 m0 gate c/t m1 m0 8a h tl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8b h tl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8c h th0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8d h th1 00 h .7 .6 .5 .4 .3 .2 .1 .0 90 h 2) p1 ff h t2 clk- out t2ex int2 int6 int5 int4 int3 91 h xpage 00 h .7 .6 .5 .4 .3 .2 .1 .0 98 h 2) scon 00 h sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf xx h t2 .6 .5 .4 .3 .2 .1 .0 a0 h 2) p2 ff h .7 .6 .5 .4 .3 .2 .1 .0 a8 h 2) ien0 00 h eal wdt et2 es et1 ex1 et0 ex0 a9 h ip0 00 h owds wdts .5 .4 .3 .2 .1 .0 aa h srell d9 h .7 .6 .5 .4 .3 .2 .1 .0 b0 h 2) p3 ff h rd wr t1 t0 int1 int0 txd rxd b1 h syscon xx10- xx01 b eale rmap xmap1 xmap0 b8 h 2) ien1 00 h exen2 swdt ex6 ex5 ex4 ex3 ex2 eadc b9 h ip1 xx00- 0000 b .5.4.3.2.1.0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers 3) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set.
c515a semiconductor group 22 1997-10-01 ba h srelh xxxx- xx11 b .1.0 c0 h 2) ircon 00 h exf2 tf2 iex6 iex5 iex4 iex3 iex2 iadc c1 h ccen 00 h coca h3 cocal 3 coca h2 cocal 2 coca h1 cocal 1 coca h0 cocal 0 c2 h ccl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c3 h cch1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c4 h ccl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c5 h cch2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c6 h ccl3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c7 h cch3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c8 h 2) t2con 00 h t2ps i3fr i2fr t2r1 t2r0 t2cm t2i1 t2i0 ca h crcl 00 h .7 .6 .5 .4 .3 .2 .1 .0 cb h crch 00 h .7 .6 .5 .4 .3 .2 .1 .0 cc h tl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cd h th2 00 h .7 .6 .5 .4 .3 .2 .1 .0 d0 h 2) psw 00 h cy ac f0 rs1 rs0 ov f1 p d8 h 2) adcon0 00 h bd clk adex bsy adm mx2 mx1 mx0 d9 h addath 00 h .9 .8 .7 .6 .5 .4 .3 .2 da h addatl 00xx- xxxx b .1.0 db h p6 .7.6.5.4.3.2.1.0 dc h adcon1 0xxx- x000 b adcl mx2mx1mx0 e0 h 2) acc 00 h .7 .6 .5 .4 .3 .2 .1 .0 e8 h 2) p4 00 h .7 .6 .5 .4 .3 .2 .1 .0 f0 h 2) b 00 h .7 .6 .5 .4 .3 .2 .1 .0 f8 h 2) p5 ff h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers table 3 contents of the sfrs, sfrs in numeric order of their addresses (cont?) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
semiconductor group 23 1997-10-01 c515a digital i/o ports the c515a allows for digital i/o on 48 lines grouped into 6 bidirectional 8-bit ports. each port bit consists of a latch, an output driver and an input buffer. read and write accesses to the i/o ports p0 through p5 are performed via their corresponding special function registers p0 to p5. the output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. in this application, port 0 outputs the low byte of the external memory address, time- multiplexed with the byte being written or read. port 2 outputs the high byte of the external memory address when the address is 16 bits wide. otherwise, the port 2 pins continue emitting the p2 sfr contents. analog input ports ports 6 is available as input port only and provides two functions. when used as digital inputs, the corresponding sfr p6 contains the digital value applied to the port 6 lines. when used for analog inputs the desired analog channel is selected by a three-bit field in sfr adcon0. of course, it makes no sense to output a value to these input-only ports by writing to the sfr p6. this will have no effect. if a digital value is to be read, the voltage levels are to be held within the input voltage specifications ( v il / v ih ). since p6 is not bit-addressable, all input lines of p6 are read at the same time by byte instructions. nevertheless, it is possible to use port 6 simultaneously for analog and digital input. however, care must be taken that all bits of p6 that have an undetermined value caused by their analog function are masked.
c515a semiconductor group 24 1997-10-01 timer / counter 0 and 1 timer/counter 0 and 1 can be used in four operating modes as listed in table 4 : in the ?imer?function (c/t = ?? the register is incremented every machine cycle. therefore the count rate is f osc /12. in the ?ounter?function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is f osc /24. external inputs int0 and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 9 illustrates the input clock logic. figure 9 timer/counter 0 and 1 input clock logic table 4 timer/counter 0 and 1 operating modes mode description tmod input clock m1 m0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler 00 f osc / 12x32 f osc / 24x32 1 16-bit timer/counter 1 1 f osc / 12 f osc / 24 2 8-bit timer/counter with 8-bit autoreload 10 3 timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer timer 1 stops 11 12 f osc /12 mcs01768 osc f c/t tmod 0 control timer 0/1 input clock tcon tr 0/1 gate tmod & =1 1 p3.4/t0 p3.5/t1 max p3.2/int0 p3.3/int1 osc /24 f 1 _ <
semiconductor group 25 1997-10-01 c515a timer/counter 2 with compare/capture/reload the timer 2 of the c515a provides additional compare/capture/reload features. which allow the selection of the following operating modes: compare : up to 4 pwm signals with 16-bit/500 ns resolution capture : up to 4 high speed capture inputs with 500 ns resolution reload : modulation of timer 2 cycle time the block diagram in figure 10 shows the general configuration of timer 2 with the additional compare/capture/reload registers. the i/o pins which can used for timer 2 control are located as multifunctional port functions at port 1. figure 10 timer 2 block diagram mcb03205 comparator ccl3/cch3 capture input/ output control p1.0/ int3/ cc0 cc1 int4/ p1.1/ cc2 int5/ p1.2/ cc3 int6/ p1.2/ ccl2/cch2 comparator ccl1/cch1 comparator crcl/crch comparator bit 16 16 bit 16 bit 16 bit osc 12 24 f osc t2ps sync. p1.7/ t2 t2ex p1.5/ sync. & t2i1 t2i0 timer 2 th2 tl2 tf2 reload exen2 reload 1 exf2 interrupt request compare _ <
c515a semiconductor group 26 1997-10-01 timer 2 operating modes the timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. a roll-over of the count value in tl2/th2 from all 1? to all 0? sets the timer overflow flag tf2 in sfr ircon, which can generate an interrupt. the bits in register t2con are used to control the timer 2 operation. timer mode: in timer function, the count rate is derived from the oscillator frequency. a prescaler offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency. gated timer mode: in gated timer function, the external input pin t2 (p1.7) functions as a gate to the input of timer 2. if t2 is high, the internal clock input is gated to the timer. t2 = 0 stops the counting procedure. this facilitates pulse width measurements. the external gate signal is sampled once every machine cycle. event counter mode: in the event counter function. the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin t2 (p1.7). in this function, the external input is sampled every machine cycle. since it takes two machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. reload of timer 2: two reload modes are selectable: in mode 0, when timer 2 rolls over from all 1? to all 0?, it not only sets tf2 but also causes the timer 2 registers to be loaded with the 16-bit value in the crc register, which is preset by software. in mode 1, a 16-bit reload from the crc register is caused by a negative transition at the corresponding input pin p1.5/t2ex. this transition will also set flag exf2 if bit exen2 in sfr ien1 has been set.
semiconductor group 27 1997-10-01 c515a timer 2 compare modes the compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. compare mode 0 in compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. it goes back to a low level on timer overflow. as long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. figure 11 shows a functional diagram of a port circuit when used in compare mode 0. the port latch is directly controlled by the timer overflow and compare match signals. the input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled. figure 11 port latch in compare mode 0 mcs02661 latch port q q clk d port pin read pin cc v read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match s r overflow timer 16 bit bit 16
c515a semiconductor group 28 1997-10-01 compare mode 1 if compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. in compare mode 1 (see figure 12 ) the port circuit consists of two separate latches. one latch (which acts as a ?hadow latch? can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs. figure 12 compare function in compare mode 1 mcs02662 latch port q q clk d read pin cc v d clk q shadow latch read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match pin port 16 bit 16 bit
semiconductor group 29 1997-10-01 c515a serial interface (usart) the serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 5 . the possible baudrates can be calculated using the formulas given in table 5 . for clarification some terms regarding the difference between ?aud rate clock?and ?aud rate should be mentioned. in the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. therefore, the baud rate generators/timers have to provide a ?aud rate clock?(output signal in figure 13 to the serial interface which - there divided by 16 - results in the actual ?aud rate? further, the abbreviation f osc refers to the oscillator frequency (crystal or external clock operation). the variable baud rates for modes 1 and 3 of the serial interface can be derived from either timer 1 or a dedicated baud rate generator (see figure 13 ). table 5 usart operating modes mode scon description sm0 sm1 0 0 0 shift register mode serial data enters and exits through r d/ t d outputs the shift clock; 8-bit are transmitted/received (lsb first); fixed baud rate 1 0 1 8-bit uart, variable baud rate 10 bits are transmitted (through t d) or received (at r d) 2 1 0 9-bit uart, fixed baud rate 11 bits are transmitted (through t d) or received (at r d) 3 1 1 9-bit uart, variable baud rate like mode 2
c515a semiconductor group 30 1997-10-01 figure 13 block diagram of baud rate generation for the serial interface table 6 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits bd and smod. table 6 serial interface - baud rate dependencies serial interface 0 operating modes active control bits baud rate calculation bd smod mode 0 (shift register) f osc / 12 mode 1 (8-bit uart) mode 3 (9-bit uart) 0 x controlled by timer 1 overflow: (2 smod timer 1 overflow rate) / 32 1 x controlled by baud rate generator (2 smod f osc ) / (64 baud rate generator overflow rate) mode 2 (9-bit uart) 0 1 f osc / 64 f osc / 32
semiconductor group 31 1997-10-01 c515a 10-bit a/d converter the c515a provides an a/d converter with the following features: 8 multiplexed input channels (port 6), which can also be used as digital inputs 10-bit resolution single or continuous conversion mode internal or external start-of-conversion trigger capability interrupt request generation after each conversion using successive approximation conversion technique via a capacitor array built-in hidden calibration of offset and linearity errors the a/d converter operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. the externally applied reference voltage range has to be held on a fixed value within the specifications. the main functional blocks of the a/d converter are shown in figure 14 .
c515a semiconductor group 32 1997-10-01 figure 14 a/d converter block diagram exen2 swdt ex5 ex6 ex2 ex3 ex4 eadc exf2 iex5 iex6 tf2 iex4 iex3 iex2 iadc adcl mx2 mx1 mx0 adcon1 (dc ) ircon (c0 ) ien1 (b8 ) h h h bd clk adex bsy adm mx2 mx1 mx0 adcon0 (d8 ) h mux s&h single/ continuous mode clock prescaler 8, 4 f osc /2 port 6 .2 .3 .4 .5 .6 .7 .8 lsb msb .1 addatl (da ) addath (d9 ) hh conversion clock input clock adc f in f aref v agnd v start of conversion write to addatl p4.0 / adst shaded bit locations are not used in adc-functions. internal bus a/d converter mcb03247 internal bus
semiconductor group 33 1997-10-01 c515a interrupt system the c515a provides 12 interrupt sources with four priority levels. five interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, a/d converter, and serial interface) and seven interrupts may be triggered externally (p3.2/int0, p3.3/int1, p1.4/int2, p1.0/int3 , p1.1/int4, p1.2/int5, p1.3/int6). the wake-up from power-down mode interrupt has a special functionality which allows to exit from the software power-down mode by a short low pulse at pin p3.2/int0 . this chapter shows the interrupt structure, the interrupt vectors and the interrupt related special function registers. figure 15 and 16 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections.
c515a semiconductor group 34 1997-10-01 figure 15 interrupt request sources (part 1) ex1 ex3 ip0.2 ip1.2 eal ex2 iex2 et0 ip1.1 ip0.1 iadc eadc ex0 ip1.0 ip0.0 ie0 ien0.0 tcon.1 0003 h h 0043 h 000b h 004b h 0013 h 0013 ien1.0 ircon.0 ien1.1 ircon.1 ien0.1 ien0.2 ien1.2 a / d converter p1.4 / nt2 ien0.7 highest priority level lowest priority level p o l l i n g s e q u e n c e mcb03248 it0 tcon.5 tf0 i2fr tcon.0 t2con.5 tcon.2 it1 tcon.3 ie1 i3fr t2con.6 ircon.2 iex3 p3.2 int0 overflow timer 0 p3.3 / int1 int3 p1.0 / cc0 bit addressable request flag is cleared by hardware
semiconductor group 35 1997-10-01 c515a figure 16 interrupt request sources (part 2) exen2 exf2 tf2 et2 et6 ip0.5 ip1.5 eal iex6 ex5 ti ri iex5 <1 es ip1.4 ip0.4 iex4 ex4 et1 ip1.3 ip0.3 tf1 ien0.3 tcon.7 001b h h 005b h 0023 h 0063 h 002b h 006b ien1.3 ircon.3 ien1.4 ircon.4 ien0.4 scon.1 scon.0 ircon.7 ircon.6 ien0.5 ien1.5 ircon.5 timer 1 overflow p1.1 / int4 / cc1 usart p1.2 / int5 / cc2 p1.5/ t2ex ien1.7 int6 / p1.3 / cc3 bit addressable request flag is cleared by hardware ien0.7 timer 2 overflow highest priority level lowest priority level p o l l i n g s e q u e n c e mcb03249 <1
c515a semiconductor group 36 1997-10-01 table 7 interrupt source and vectors interrupt source interrupt vector address interrupt request flags external interrupt 0 0003 h ie0 timer 0 overflow 000b h tf0 external interrupt 1 0013 h ie1 timer 1 overflow 001b h tf1 serial channel 0023 h ri / ti timer 2 overflow / ext. reload 002b h tf2 / exf2 a/d converter 0043 h iadc external interrupt 2 004b h iex2 external interrupt 3 0053 h iex3 external interrupt 4 005b h iex4 external interrupt 5 0063 h iex5 external interrupt 6 006b h iex6 wake-up from power-down mode 007b h
semiconductor group 37 1997-10-01 c515a fail save mechanisms the c515a offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: a programmable watchdog timer (wdt), with variable time-out period from 512 m s up to approx. 1.1 s at 12 mhz (256 m s up to approx. 0.65 s at 24 mhz) an oscillator watchdog (owd) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. the watchdog timer in the c515a is a 15-bit timer, which is incremented by a count rate of f osc /24 up to f osc /384. the system clock of the c515a is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. for programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. figure 15 shows the block diagram of the watchdog timer unit. figure 17 block diagram of the watchdog timer the watchdog timer can be started by software (bit swdt) or by hardware through pin pe /swd, but it cannot be stopped during active mode of the c515a. if the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. for refreshing of the watchdog timer the content of the sfr wdtrel is transferred to the upper 7-bit of the watchdog timer. the refresh sequence consists of two consecutive instructions which set the bits wdt and swdt each. the reset cause (external reset or reset caused by the watchdog) can be examined by software (flag wdts). it must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. mcb03250 ip0 (a9 ) h osc f wdts - ------ 2 16 14 07 8 wdtl wdth /12 external hw reset external hw power-down pe/swd control logic ien0 (a8 ) h ien1 (b8 ) h 6 70 wdt reset-request wdtpsel wdtrel (86 ) h - wdt -- - - -- - swdt -- - - --
c515a semiconductor group 38 1997-10-01 oscillator watchdog the oscillator watchdog unit serves for four functions: monitoring of the on-chip oscillator's function the watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary rc oscillator in the watchdog unit, the internal clock is supplied by the rc oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-chip oscillator has a higher frequency than the rc oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. fast internal reset after power-on the oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. the oscillator watchdog unit also works identically to the monitoring function. restart from the hardware power down mode. if the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. the oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function. control of external wake-up from software power-down mode when the software power-down mode is left by a low level at the p3.2/int0 pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. in the power-down mode the rc oscillator and the on-chip oscillator are stopped. both oscillators are started again when power-down mode is released. when the on-chip oscillator has a higher frequency than the rc oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.
semiconductor group 39 1997-10-01 c515a figure 18 block diagram of the oscillator watchdog int. clock xtal2 xtal1 owds mcb03251 ip0 (a9 ) h rc oscillator oscillator on-chip f rc delay 1 f 2 f 2 f 1 f < frequency comparator logic control p3.2 / int0 >1 logic control start / stop start / stop 2 ewpd (pcon1.0) mode activated power-down power-down mode wake-up interrupt internal reset 5 3 mhz
c515a semiconductor group 40 1997-10-01 power saving modes the c515a provides two basic power saving modes, the idle mode and the power down mode. additionally, a slow down mode is available. this power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. idle mode the cpu is gated off from the oscillator. all peripherals are still provided with the clock and are able to work. idle mode is entered by software and can be left by an interrupt or reset. slow down mode the controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 8. this slows down all parts of the controller, the cpu and all peripherals, to 1/8th of their normal operating frequency and also reduces power consumption. software power down mode the operation of the c515 is completely stopped and the oscillator is turned off. this mode is used to save the contents of the internal ram with a very low standby current. this power down mode is entered by software and can be left by reset or by a short low pulse at pin p3.2/ int0 . hardware power down mode if pin hwpd gets active (low level) the part enters the hardware power down mode and starts a complete internal reset sequence. thereafter, both oscillators of the chip are stopped and the port pins and several control lines enter a floating state. in the power down mode of operation, v cc can be reduced to minimize power consumption. it must be ensured, however, that v cc is not reduced before the power down mode is invoked, and that v cc is restored to its normal operating level, before the power down mode is terminated. table 8 gives a general overview of the entry and exit procedures of the power saving modes.
semiconductor group 41 1997-10-01 c515a table 8 power saving modes overview mode entering 2-instruction example leaving by remarks idle mode orl pcon, #01h orl pcon, #20h occurrence of an interrupt from a peripheral unit cpu clock is stopped; cpu maintains their data; peripheral units are active (if enabled) and provided with clock hardware reset slow down mode in normal mode: orl pcon,#10h anl pcon,#0efh or hardware reset internal clock rate is reduced to 1/8 of its nominal frequency with idle mode: orl pcon,#01h orl pcon, #30h occurrence of an interrupt from a peripheral unit cpu clock is stopped; cpu maintains their data; peripheral units are active (if enabled) and provided with 1/8 of its nominal frequency hardware reset software power down mode orl pcon, #02h orl pcon, #40h hardware reset oscillator is stopped; contents of on-chip ram and sfr? are maintained; short low pulse at pin p3.2/int0 hardware power down mode hwpd = 0 hwpd = 1 oscillator is stopped; internal reset is executed;
c515a semiconductor group 42 1997-10-01 absolute maximum ratings ambient temperature under bias ( t a ) ......................................................... ?40 to + 125 c storage temperature ( t stg ) .......................................................................... ?65 c to 150 c voltage on v cc pins with respect to ground ( v ss ) ....................................... ?0.5 v to 6.5 v voltage on any pin with respect to ground ( v ss ) ......................................... ?0.5 v to v cc +0.5 v input current on any pin during overload condition..................................... ?10 ma to 10 ma absolute sum of all input currents during overload condition ..................... i 100 ma i power dissipation of package ..................................................................... tbd note: stresses above those listed under ?bsolute maximum ratings?may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during overload conditions ( v in > v cc or v in < v ss ) the voltage on v cc pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings.
semiconductor group 43 1997-10-01 c515a dc characteristics v cc = 5 v + 10%, ?15%; v ss = 0 v t a = 0 to 70 c for the sab-c515a t a = ?40 to 85 c for the saf-c515a t a = ?40 to 110 c for the sah-c515a t a = ?40 to 125 c for the sak-c515a notes see next page parameter symbol limit values unit test condition min. max. input low voltage pins except ea ,reset ,hwpd ea pin hwpd and reset pins v il v il1 v il2 ?0.5 ?0.5 ?0.5 0.2 v cc ?0.1 0.2 v cc ?0.3 0.2 v cc + 0.1 v v v input high voltage pins except reset , xtal2 and hwpd xtal2 pin reset and hwpd pin v ih v ih1 v ih2 0.2 v cc + 0.9 0.7 v cc 0.6 v cc v cc + 0.5 v cc + 0.5 v cc + 0.5 v v v output low voltage ports 1, 2, 3, 4, 5 port 0, ale, psen v ol v ol1 0.45 0.45 v v i ol = 1.6 ma 1) i ol = 3.2 ma 1) output high voltage ports 1, 2, 3, 4, 5 port 0 in external bus mode, ale, psen v oh v oh1 2.4 0.9 v cc 2.4 0.9 v cc v v v v i oh = ?80 m a i oh = ?10 m a i oh = ?800 m a 2) i oh = ?80 m a 2) logic 0 input current ports 1, 2, 3, 4, 5 i li ?10 ?70 m a v i n = 0.45 v logical 0-to-1 transition current, ports 1, 2, 3, 4, 5 i tl ?65 ?650 m a v i n = 2 v input leakage current port 0 and 6, ea , hwpd i li ? 1 m a 0.45 < v i n < v cc input low current to reset for reset xtal2 pe /swd i il2 i il3 i il4 ?10 ?100 ?15 ?20 m a m a m a v in = 0.45 v v i n = 0.45 v v i n = 0.45 v pin capacitance c io ?10 pf f c = 1 mhz, t a = 25 c overload current i ov 5ma 8) 9)
c515a semiconductor group 44 1997-10-01 power supply current notes: 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case (capacitive loading > 100 pf), the noise pulse on ale line may exceed 0.8 v. in such cases it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v cc specification when the address lines are stabilizing. 3) i pd (software power-down mode) is measured under following conditions: ea = reset = port 0 = port 6 = v cc ; xtal1 = n.c.; xtal2 = v ss ; pe /swd = v ss ; hwpd = v cc ; v agnd = v ss ; v aref = v cc ; all other pins are disconnected. i pd (hardware power-down mode): independent from any particular pin connection. 4) i cc (active mode) is measured with: xtal2 driven with t clch , t chcl = 5 ns , v il = v ss + 0.5 v, v ih = v cc ?0.5 v; xtal1 = n.c.; ea = pe /swd = port 0 = port 6 = v cc ; hwpd = v cc ; reset = v ss ; all other pins are disconnected. i cc would be slightly higher if a crystal oscillator is used (appr. 1 ma). 5) i cc (idle mode) is measured with all output pins disconnected and with all peripherals disabled; xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v cc ?0.5 v; xtal1 = n.c.; reset = v cc ; hwpd = port 0 = port 6 = v cc ; ea = pe /swd = v ss ; all other pins are disconnected; 6) i cc (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v cc ?0.5 v; xtal1 = n.c.; reset = v cc ; hwpd = port 6 = v cc ; ea = pe /swd = v ss ; all other pins are disconnected; the microcontroller is put into slow-down mode by software; 7) i cc (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v cc ?0.5 v; xtal1 = n.c.; reset = v cc ; hwpd = port 6 = v cc ; ea = pe /swd = v ss ; all other pins are disconnected; the microcontroller is put into idle mode with slow-down mode enabled by software; 8) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v cc + 0.5 v or v ov < v ss - 0.5 v). the supply voltage v cc and v ss must remain within the specified limits. the absolute sum of input currents on all port pins may not exceed 50 ma. 9) not 100% tested, guaranteed by design characterization 10)the typical i cc values are periodically measured at t a = +25 ?c and v cc = 5 v but not 100% tested. 11)the maximum i cc values are measured under worst case conditions ( t a = 0 ?c or -40 ?c and v cc = 5.5 v) parameter symbol limit values unit test condition typ. 10) max. 11) active mode 18 mhz 24 mhz i cc i cc 16.9 21.7 23.1 29.4 ma ma 4) idle mode 18 mhz 24 mhz i cc i cc 8.5 11.0 12.1 15.0 ma ma 5) active mode with slow-down enabled 18 mhz 24 mhz i cc i cc 5.6 6.6 8.0 9.6 ma ma 6) active mode with slow-down enabled 18 mhz 24 mhz i cc i cc 3.0 3.3 4.1 4.7 ma ma 7) power-down mode i pd 10 50 m a v cc = 2 ? 5.5 v 3)
semiconductor group 45 1997-10-01 c515a figure 19 icc diagram note : f osc is the oscillator frequency in mhz. i cc values are given in ma. table 9 power supply current calculation formulas parameter symbol formula active mode i cc typ i cc max 0.79 * f osc + 2.7 1.04 * f osc + 4.4 idle mode i cc typ i cc max 0.43 * f osc + 0.7 0.48 * f osc + 3.5 active mode with slow-down enabled i cc typ i cc max 0.17 * f osc + 2.5 0.28 * f osc + 2.9 idle mode with slow-down enabled i cc typ i cc max 0.06 * f osc + 1.9 0.09 * f osc + 2.5 cc i 0 0 osc f mcd03252 mhz 24 ma active mode active mode idle mode idle mode cc max i cc typ i active + slow down mode idle + slow down mode 4 8 12 16 20 5 10 15 20 25 30
c515a semiconductor group 46 1997-10-01 a/d converter characteristics v cc = 5 v + 10%, ?15%; v ss = 0 v t a = 0 to 70 c for the sab-c515a t a = ?40 to 85 c for the saf-c515a t a = ?40 to 110 c for the sah-c515a t a = ?40 to 125 c for the sak-c515a 4 v v aref v cc + 0.1 v; v ss ?0.1 v v agnd v ss + 0.2 v notes see next page. clock calculation table: further timing conditions: t adc min = 500 ns t in = 2 / f osc = 2 t clcl parameter symbol limit values unit test condition min. max. analog input voltage v ain v agnd v aref v 1) sample time t s 16 t in 8 t in ns prescaler ? 8 prescaler ? 4 2) conversion cycle time t adcc 96 t in 48 t in ns prescaler ? 8 prescaler ? 4 3) total unadjusted error t ue 2 lsb v ss + 0.5 v v in v cc ?0.5 v 4) internal resistance of reference voltage source r aref t adc / 250 ?1 k w t adc in [ns] 5) 6) internal resistance of analog source r asrc t s / 500 ?0.8 k w t s in [ns] 2) 6) adc input capacitance c ain ?0pf 6) clock prescaler ratio adcl t adc t s t adcc ? 8 1 8 t in 16 t in 96 t in ? 4 0 4 t in 8 t in 48 t in
semiconductor group 47 1997-10-01 c515a notes: 1) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 2) during the sample time the input capacitance c ain can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach their final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. 3) this parameter includes the sample time t s , the time for determining the digital result and the time for the calibration. values for the conversion clock t adc depend on programming and can be taken from the table on the previous page. 4) t ue is tested at v aref = 5.0 v, v agnd = 0 v, v cc = 4.9 v. it is guaranteed by design characterization for all other voltages within the defined voltage range. if an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma, an additional conversion error of 1/2 lsb is permissible. 5) during the conversion the adc? capacitance must be repeatedly charged or discharged. the internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. the maximum internal resistance results from the programmed conversion timing. 6) not 100% tested, but guaranteed by design characterization.
c515a semiconductor group 48 1997-10-01 ac characteristics (18 mhz) v cc = 5 v + 10%, ?15%; v ss = 0 v t a = 0 to 70 c for the sab-c515a t a = ?40 to 85 c for the saf-c515a t a = ?40 to 110 c for the sah-c515a t a = ?40 to 125 c for the sak-c515a ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c515a to devices with float times up to 48 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 18 mhz clock variable clock 1/ t clcl = 3.5 mhz to 18 mhz min. max. min. max. ale pulse width t lhll 71 2 t clcl ?40 ns address setup to ale t avll 26 t clcl ?30 ns address hold after ale t llax 26 t clcl ?30 ns ale low to valid instruction in t lliv 122 4 t clcl ?100 ns ale to psen t llpl 31 t clcl ?25 ns psen pulse width t plph 132 3 t clcl ?35 ns psen to valid instruction in t pliv ?2 3 t clcl ?75 ns input instruction hold after psen t pxix 00?s input instruction float after psen t pxiz *) ?6 t clcl ?10 ns address valid after psen t pxav *) 48 t clcl ?8 ns address to valid instr in t aviv 180 5 t clcl ?98 ns address float to psen t azpl 00?s
semiconductor group 49 1997-10-01 c515a ac characteristics (18 mhz, cont?) external data memory characteristics external clock drive characteristics parameter symbol limit values unit 18 mhz clock variable clock 1/ t clcl = 3.5 mhz to 18 mhz min. max. min. max. rd pulse width t rlrh 233 6 t clcl ?100 ns wr pulse width t wlwh 233 6 t clcl ?100 ns address hold after ale t llax2 81 2 t clcl ?30 ns rd to valid data in t rldv 128 5 t clcl ?150 ns data hold after rd t rhdx 00?s data float after rd t rhdz ?1 2 t clcl ?60 ns ale to valid data in t lldv 294 8 t clcl ?150 ns address to valid data in t avdv 335 9 t clcl ?165 ns ale to wr or rd t llwl 117 217 3 t clcl ?50 3 t clcl + 50 ns address valid to wr or rd t avwl 92 4 t clcl ?130 ns wr or rd high to ale high t whlh 16 96 t clcl ?40 t clcl + 40 ns data valid to wr transition t qvwx 11 t clcl ?45 ns data setup before wr t qvwh 239 7 t clcl ?150 ns data hold after wr t whqx 16 t clcl ?40 ns address float after rd t rlaz 0?ns parameter symbol limit values unit variable clock freq. = 3.5 mhz to 18 mhz min. max. oscillator period t clcl 55.6 285.7 ns high time t chcx 15 t clcl ? t clcx ns low time t clcx 15 t clcl ? t chcx ns rise time t clch ?5ns fall time t chcl ?5ns
c515a semiconductor group 50 1997-10-01 ac characteristics (24 mhz) v cc = 5 v + 10%, ?15%; v ss = 0 v t a = 0 to 70 c for the sab-c515a t a = ?40 to 85 c for the saf-c515a t a = ?40 to 110 c for the sah-c515a ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c515a to devices with float times up to 37 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 24 mhz clock variable clock 1/ t clcl = 3.5 mhz to 24 mhz min. max. min. max. ale pulse width t lhll 43 2 t clcl ?40 ns address setup to ale t avll 17 t clcl ?25 ns address hold after ale t llax 17 t clcl ?25 ns ale low to valid instruction in t lliv ?0 4 t clcl ?87 ns ale to psen t llpl 22 t clcl ?20 ns psen pulse width t plph 95 3 t clcl ?30 ns psen to valid instruction in t pliv ?0 3 t clcl ?65 ns input instruction hold after psen t pxix 00?s input instruction float after psen t pxiz *) ?2 t clcl ?10 ns address valid after psen t pxav *) 37 t clcl ?5 ns address to valid instr in t aviv 148 5 t clcl ?60 ns address float to psen t azpl 00?s
semiconductor group 51 1997-10-01 c515a ac characteristics (24 mhz, cont?) external data memory characteristics external clock drive characteristics parameter symbol limit values unit 24 mhz clock variable clock 1/ t clcl = 3.5 mhz to 24 mhz min. max. min. max. rd pulse width t rlrh 180 6 t clcl ?70 ns wr pulse width t wlwh 180 6 t clcl ?70 ns address hold after ale t llax2 56 2 t clcl ?27 ns rd to valid data in t rldv 118 5 t clcl ?90 ns data hold after rd t rhdx 00?s data float after rd t rhdz ?3 2 t clcl ?20 ns ale to valid data in t lldv 200 8 t clcl ?133 ns address to valid data in t avdv 220 9 t clcl ?155 ns ale to wr or rd t llwl 75 175 3 t clcl ?50 3 t clcl + 50 ns address valid to wr or rd t avwl 67 4 t clcl ?97 ns wr or rd high to ale high t whlh 17 67 t clcl ?25 t clcl + 25 ns data valid to wr transition t qvwx 5 t clcl ?37 ns data setup before wr t qvwh 170 7 t clcl ?122 ns data hold after wr t whqx 15 t clcl ?27 ns address float after rd t rlaz 0?ns parameter symbol limit values unit variable clock freq. = 3.5 mhz to 24 mhz min. max. oscillator period t clcl 41.7 285.7 ns high time t chcx 12 t clcl ? t clcx ns low time t clcx 12 t clcl ? t chcx ns rise time t clch ?2ns fall time t chcl ?2ns
c515a semiconductor group 52 1997-10-01 figure 20 program memory read cycle mct00096 ale psen port 2 lhll t a8 - a15 a8 - a15 a0 - a7 instr.in a0 - a7 port 0 t avll plph t t llpl t lliv t pliv t azpl t llax t pxiz t pxix t aviv t pxav
semiconductor group 53 1997-10-01 c515a figure 21 data memory read cycle mct00097 ale psen port 2 whlh t port 0 rd t lldv t rlrh t llwl t rldv t avll t llax2 t rlaz t avwl t avdv t rhdx t rhdz a0 - a7 from ri or dpl from pcl a0 - a7 instr. in data in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph
c515a semiconductor group 54 1997-10-01 figure 22 data memory write cycle figure 23 external clock drive on xtal2 mct00098 ale psen port 2 whlh t port 0 wr t wlwh t llwl t qvwx t avll t llax2 t qvwh t avwl t whqx a0 - a7 from ri or dpl from pcl a0 - a7 instr.in data out a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph mct00033 t chcx t clcx chcl t clch t v cc t clcl - 0.5v 0.45v cc 0.7 v v - 0.1 cc 0.2
semiconductor group 55 1997-10-01 c515a rom verification characteristics for the c515a-1rm rom verification mode 1 figure 24 rom verification mode 1 parameter symbol limit values unit min. max. address to valid data t avqv 10 t clcl ns p1.0-p1.7 p2.0-p2.6 port 0 mcs03253 address new address new data out data out t avqv data: addresses: p0.0-p0.7 p1.0-p1.7 p2.0-p2.6 = = = d0-d7 a0-a7 a8-a14 v reset = il2 psen inputs: = = ale, ea ss v v ih
c515a semiconductor group 56 1997-10-01 rom verification mode 2 figure 25 rom verification mode 2 parameter symbol limit values unit min. typ max. ale pulse width t awd 2 t clcl ns ale period t acy 12 t clcl ?s data valid after ale t dva 4 t clcl ns data stable after ale t dsa 8 t clcl ns p3.5 setup to ale low t as t clcl ?s oscillator frequency 1/ t clcl 3.5 24 mhz mct02613 t acy t awd t dsa dva t t as data valid ale port 0 p3.5
semiconductor group 57 1997-10-01 c515a figure 26 ac testing: input, output waveforms figure 27 ac testing : float waveforms figure 28 recommended oscillator circuits for crystal oscillator ac inputs during testing are driven at v cc - 0.5 v for a logic ??and 0.45 v for a logic ?? timing measurements are made at v ihmin for a logic ??and v ilmax for a logic ?? 0.45 v v cc 0.2 -0.1 +0.9 0.2 cc v test points mct00039 v cc -0.5 v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh / v ol level occurs. i ol / i oh 3 20 ma mct00038 v load v load -0.1 v +0.1 v load v timing reference points v oh -0.1 v +0.1 v ol v mcs03245 c c 3.5 - 24 mhz xtal1 xtal2 xtal2 xtal1 n.c. external oscillator signal crystal oscillator mode driving from external source crystal mode: c = 20 pf 10 pf (incl. stray capacitance)
c515a semiconductor group 58 1997-10-01 figure 29 p-mqfp-80-1 package outline gpm05249 plastic package, p-mqfp-80-1 (smd) (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information dimensions in mm smd = surface mounted device

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